SHORT CBOX related data and metrics

EVENTSET
FIXC0 INSTR_RETIRED_ANY
FIXC1 CPU_CLK_UNHALTED_CORE
FIXC2 CPU_CLK_UNHALTED_REF
CBOX0C0 LLC_VICTIMS_M
CBOX1C0 LLC_VICTIMS_M
CBOX2C0 LLC_VICTIMS_M
CBOX3C0 LLC_VICTIMS_M
CBOX4C0 LLC_VICTIMS_M
CBOX5C0 LLC_VICTIMS_M
CBOX6C0 LLC_VICTIMS_M
CBOX7C0 LLC_VICTIMS_M
CBOX8C0 LLC_VICTIMS_M
CBOX9C0 LLC_VICTIMS_M
CBOX10C0 LLC_VICTIMS_M
CBOX11C0 LLC_VICTIMS_M
CBOX12C0 LLC_VICTIMS_M
CBOX13C0 LLC_VICTIMS_M
CBOX14C0 LLC_VICTIMS_M
CBOX15C0 LLC_VICTIMS_M
CBOX16C0 LLC_VICTIMS_M
CBOX17C0 LLC_VICTIMS_M
CBOX0C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX1C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX2C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX3C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX4C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX5C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX6C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX7C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX8C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX9C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX10C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX11C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX12C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX13C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX14C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX15C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX16C1:STATE=0x1 LLC_LOOKUP_ANY
CBOX17C1:STATE=0x1 LLC_LOOKUP_ANY

METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz]  1.E-06*(FIXC1/FIXC2)/inverseClock
CPI  FIXC1/FIXC0
LLC misses per instruction (CBOX0C0+CBOX1C0+CBOX2C0+CBOX3C0+CBOX4C0+CBOX5C0+CBOX6C0+CBOX7C0+CBOX8C0+CBOX9C0+CBOX10C0+CBOX11C0+CBOX12C0+CBOX13C0+CBOX14C0+CBOX15C0+CBOX16C0+CBOX17C0)/FIXC0
LL2 data written to MEM [MBytes] 1E-6*(CBOX0C1:STATE=0x1+CBOX1C1:STATE=0x1+CBOX2C1:STATE=0x1+CBOX3C1:STATE=0x1+CBOX4C1:STATE=0x1+CBOX5C1:STATE=0x1+CBOX6C1:STATE=0x1+CBOX7C1:STATE=0x1+CBOX8C1:STATE=0x1+CBOX9C1:STATE=0x1+CBOX10C1:STATE=0x1+CBOX11C1:STATE=0x1+CBOX12C1:STATE=0x1+CBOX13C1:STATE=0x1+CBOX14C1:STATE=0x1+CBOX15C1:STATE=0x1+CBOX16C1:STATE=0x1+CBOX17C1:STATE=0x1)*64


LONG
Formulas:
LLC Misses Per Instruction = sum(LLC_VICTIMS_M)/INSTR_RETIRED_ANY
LL2 data written to MEM [MBytes] = sum(LLC_LOOKUP_ANY)*64*1E-6
-
The CBOXes mediate the traffic from the L2 cache to the segmented L3 cache. Each
CBOX is responsible for one segment (2.5 MByte). The boxes maintain the coherence between all
CPU cores of the socket. Depending on the CPU core count, some CBOXes are not attached
to a 2.5 MByte slice but are still active and track the traffic.
