# =======================================================================================
#
#      Filename:  perfmon_icelakeX_events.txt
#
#      Description:  Event list for Intel Icelake X
#
#      Version:   5.1.0
#      Released:  20.11.2020
#
#      Author:   Thomas Gruber (tr), thomas.roehl@googlemail.com
#      Project:  likwid
#
#      Copyright (C) 2020 RRZE, University Erlangen-Nuremberg
#
#      This program is free software: you can redistribute it and/or modify it under
#      the terms of the GNU General Public License as published by the Free Software
#      Foundation, either version 3 of the License, or (at your option) any later
#      version.
#
#      This program is distributed in the hope that it will be useful, but WITHOUT ANY
#      WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
#      PARTICULAR PURPOSE.  See the GNU General Public License for more details.
#
#      You should have received a copy of the GNU General Public License along with
#      this program.  If not, see <http://www.gnu.org/licenses/>.
#
# =======================================================================================

EVENT_TEMP_CORE          0x00   TMP0
UMASK_TEMP_CORE          0x00

EVENT_PWR_PKG_ENERGY          0x02   PWR0
UMASK_PWR_PKG_ENERGY          0x00

EVENT_PWR_PP0_ENERGY          0x01   PWR1
UMASK_PWR_PP0_ENERGY          0x00

EVENT_PWR_PP1_ENERGY          0x04   PWR2
UMASK_PWR_PP1_ENERGY          0x00

EVENT_PWR_DRAM_ENERGY          0x03   PWR3
UMASK_PWR_DRAM_ENERGY          0x00

EVENT_PWR_PLATFORM_ENERGY          0x05   PWR4
UMASK_PWR_PLATFORM_ENERGY          0x00

EVENT_VOLTAGE_CORE          0x00   VTG0
UMASK_VOLTAGE_CORE          0x00

EVENT_INSTR_RETIRED              0x00   FIXC0
UMASK_INSTR_RETIRED_ANY          0x00

EVENT_CPU_CLK_UNHALTED           0x00   FIXC1
UMASK_CPU_CLK_UNHALTED_CORE      0x00

EVENT_CPU_CLK_UNHALTED           0x00   FIXC2
UMASK_CPU_CLK_UNHALTED_REF       0x00

EVENT_TOPDOWN_SLOTS                0x00   FIXC3
UMASK_TOPDOWN_SLOTS                0x00

EVENT_RETIRING                 0x00 TMA0
UMASK_RETIRING                 0x00

EVENT_BAD_SPECULATION          0x00 TMA1
UMASK_BAD_SPECULATION          0x00

EVENT_FRONTEND_BOUND           0x00 TMA2
UMASK_FRONTEND_BOUND           0x00

EVENT_BACKEND_BOUND            0x00 TMA3
UMASK_BACKEND_BOUND            0x00

EVENT_LD_BLOCKS                         0x03 PMC
UMASK_LD_BLOCKS_STORE_FORWARD           0x02
UMASK_LD_BLOCKS_NO_SR                   0x08

EVENT_LD_BLOCKS_PARTIAL_ADDRESS_ALIAS   0x07 PMC
UMASK_LD_BLOCKS_PARTIAL_ADDRESS_ALIAS   0x01

EVENT_DTLB_LOAD_MISSES                      0x08 PMC
#UMASK_DTLB_LOAD_MISSES_CAUSES_A_WALK        0x01
UMASK_DTLB_LOAD_MISSES_WALK_PENDING         0x10
UMASK_DTLB_LOAD_MISSES_STLB_HIT             0x20
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED       0x0E
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_4K    0x02
UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_2M_4M 0x04
#UMASK_DTLB_LOAD_MISSES_WALK_COMPLETED_1G    0x08
DEFAULT_OPTIONS_DTLB_LOAD_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_DTLB_LOAD_MISSES_WALK_ACTIVE          0x10

EVENT_DTLB_STORE_MISSES                      0x49 PMC
#UMASK_DTLB_STORE_MISSES_CAUSES_A_WALK        0x01
UMASK_DTLB_STORE_MISSES_WALK_PENDING         0x10
UMASK_DTLB_STORE_MISSES_STLB_HIT             0x20
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED       0x0E
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_4K    0x02
UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_2M_4M 0x04
#UMASK_DTLB_STORE_MISSES_WALK_COMPLETED_1G    0x08
DEFAULT_OPTIONS_DTLB_STORE_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_DTLB_STORE_MISSES_WALK_ACTIVE          0x10

EVENT_INT_MISC                          0x0D PMC
UMASK_INT_MISC_RECOVERY_CYCLES          0x01
DEFAULT_OPTIONS_INT_MISC_ALL_RECOVERY_CYCLES EVENT_OPTION_THRESHOLD=0x1
UMASK_INT_MISC_ALL_RECOVERY_CYCLES      0x03
UMASK_INT_UOP_DROPPING                  0x10
UMASK_INT_CLEAR_RESTEER_CYCLES          0x80

EVENT_UOPS_ISSUED                0x0E  PMC
UMASK_UOPS_ISSUED_ANY            0x01
DEFAULT_OPTIONS_UOPS_ISSUED_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
UMASK_UOPS_ISSUED_STALL_CYCLES   0x01

EVENT_ARITH_DIVIDER                     0x14 PMC
DEFAULT_OPTIONS_ARITH_DIVIDER_ACTIVE    EVENT_OPTION_THRESHOLD=0x1
UMASK_ARITH_DIVIDER_ACTIVE              0x01
# Added by me
DEFAULT_OPTIONS_ARITH_DIVIDER_COUNT     EVENT_OPTION_EDGE=0x1,EVENT_OPTION_THRESHOLD=0x1
UMASK_ARITH_DIVIDER_COUNT               0x01

EVENT_L2_RQSTS                          0x24 PMC
UMASK_L2_RQSTS_DEMAND_DATA_RD_MISS      0x21
UMASK_L2_RQSTS_RFO_MISS                 0x22
UMASK_L2_RQSTS_CODE_RD_MISS             0x24
UMASK_L2_RQSTS_ALL_DEMAND_MISS          0x27
UMASK_L2_RQSTS_SWPF_MISS                0x28
UMASK_L2_RQSTS_DEMAND_DATA_RD_HIT       0xC1
UMASK_L2_RQSTS_RFO_HIT                  0xC2
UMASK_L2_RQSTS_CODE_RD_HIT              0xC4
UMASK_L2_RQSTS_SWPF_HIT                 0xC8
UMASK_L2_RQSTS_ALL_DEMAND_DATA_RD       0xE1
UMASK_L2_RQSTS_ALL_RFO                  0xE2
UMASK_L2_RQSTS_ALL_CODE_RD              0xE4
UMASK_L2_RQSTS_ALL_DEMAND_REFERENCES    0xE7

EVENT_CORE_POWER                        0x28 PMC
UMASK_CORE_POWER_LVL0_TURBO_LICENSE     0x07
UMASK_CORE_POWER_LVL1_TURBO_LICENSE     0x18
UMASK_CORE_POWER_LVL2_TURBO_LICENSE     0x20

EVENT_LONGEST_LAT_CACHE                 0x2E PMC
UMASK_LONGEST_LAT_CACHE_MISS            0x01

EVENT_SW_PREFETCH_ACCESS            0x32 PMC
UMASK_SW_PREFETCH_ACCESS_NTA        0x01
UMASK_SW_PREFETCH_ACCESS_T0         0x02
UMASK_SW_PREFETCH_ACCESS_T1_T2      0x04
UMASK_SW_PREFETCH_ACCESS_PREFETCHW  0x08

EVENT_CPU_CLOCK_UNHALTED                    0x3C   PMC
UMASK_CPU_CLOCK_UNHALTED_THREAD_P           0x00
UMASK_CPU_CLOCK_UNHALTED_REF_XCLK           0x01
UMASK_CPU_CLOCK_UNHALTED_ONE_THREAD_ACTIVE  0x02
UMASK_CPU_CLOCK_UNHALTED_REF_DISTRIBUTED    0x08

EVENT_L1D_PEND_MISS                     0x48 PMC
UMASK_L1D_PEND_MISS_PENDING             0x01
UMASK_L1D_PEND_MISS_FB_FULL             0x02
DEFAULT_OPTIONS_L1D_PEND_MISS_PENDING_CYCLES EVENT_OPTION_THRESHOLD=0x1
UMASK_L1D_PEND_MISS_PENDING_CYCLES      0x01
DEFAULT_OPTIONS_L1D_PEND_MISS_FB_FULL_PERIODS EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=1
UMASK_L1D_PEND_MISS_FB_FULL_PERIODS     0x02
UMASK_L1D_PEND_MISS_L2_STALL            0x4

EVENT_LOAD_HIT_PREFETCH                 0x4C PMC
UMASK_LOAD_HIT_PREFETCH_SWPF            0x01

EVENT_L1D                               0x51 PMC
UMASK_L1D_REPLACEMENT                   0x01
#UMASK_L1D_M_EVICT                       0x04

EVENT_TX_MEM                                                0x54 PMC
UMASK_TX_MEM_ABORT_CONFLICT                                 0x01
UMASK_TX_MEM_ABORT_CAPACITY_WRITE                           0x02
UMASK_TX_MEM_ABORT_CAPACITY_READ                            0x80
UMASK_TX_MEM_ABORT_HLE_STORE_TO_ELIDED_LOCK                 0x04
UMASK_TX_MEM_ABORT_HLE_ELISION_BUFFER_NOT_EMPTY             0x08
UMASK_TX_MEM_ABORT_HLE_ELISION_BUFFER_MISMATCH              0x10
UMASK_TX_MEM_ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT 0x20
UMASK_TX_MEM_HLE_ELISION_BUFFER_FULL                        0x40

EVENT_TX_EXEC                           0x5D PMC
UMASK_TX_EXEC_MISC2                     0x02
UMASK_TX_EXEC_MISC3                     0x04

EVENT_RS_EVENTS_EMPTY                   0x5E PMC
UMASK_RS_EVENTS_EMPTY_CYCLES            0x01
DEFAULT_OPTIONS_RS_EVENTS_EMPTY_END     EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=0x1,EVENT_OPTION_EDGE=0x1
UMASK_RS_EVENTS_EMPTY_END               0x01

EVENT_OFFCORE_REQUESTS_OUTSTANDING                                          0x60 PMC
UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD                           0x01
#DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD EVENT_OPTION_THRESHOLD=0x1
#UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD               0x01
#DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD_GE_6 EVENT_OPTION_THRESHOLD=0x6
#UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_DATA_RD_GE_6          0x01
#UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_CODE_RD                           0x02
#DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD EVENT_OPTION_THRESHOLD=0x1
#UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_CODE_RD               0x02
UMASK_OFFCORE_REQUESTS_OUTSTANDING_DEMAND_RFO                               0x04
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DEMAND_RFO                   0x04
UMASK_OFFCORE_REQUESTS_OUTSTANDING_ALL_DATA_RD                              0x08
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_DATA_RD                      0x08
DEFAULT_OPTIONS_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_L3_MISS_DEMAND_DATA_RD EVENT_OPTION_THRESHOLD=0x1
UMASK_OFFCORE_REQUESTS_OUTSTANDING_CYCLES_WITH_L3_MISS_DEMAND_DATA_RD       0x10

EVENT_IDQ                               0x79 PMC
UMASK_IDQ_MITE_UOPS                     0x04
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_OK EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_MITE_CYCLES_OK                0x04
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x1 # Should this also be 1 for Tigerlake?
UMASK_IDQ_MITE_CYCLES_ANY               0x04
UMASK_IDQ_DSB_UOPS                      0x08
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_OK EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_DSB_CYCLES_OK                 0x08
DEFAULT_OPTIONS_IDQ_DSB_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_DSB_CYCLES_ANY                0x08
UMASK_IDQ_MS_UOPS                       0x30
DEFAULT_OPTIONS_IDQ_MS_SWITCHES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=1
UMASK_IDQ_MS_SWITCHES                   0x30
DEFAULT_OPTIONS_IDQ_MITE_CYCLES_ANY EVENT_OPTION_THRESHOLD=0x1
UMASK_IDQ_MS_CYCLES_ANY                 0x30

EVENT_ICACHE_16B_IFDATA_STALL    0x80 PMC
UMASK_ICACHE_16B_IFDATA_STALL    0x04

EVENT_ICACHE_64B_IFTAG           0x83 PMC
UMASK_ICACHE_64B_IFTAG_HIT       0x01
UMASK_ICACHE_64B_IFTAG_MISS      0x02
# Added by me to cover HIT & MISS
UMASK_ICACHE_64B_IFTAG_ALL       0x03
UMASK_ICACHE_64B_IFTAG_STALL     0x04

EVENT_ITLB_MISSES                       0x85 PMC
#UMASK_ITLB_MISSES_CAUSES_A_WALK         0x01
UMASK_ITLB_MISSES_WALK_PENDING          0x10
UMASK_ITLB_MISSES_STLB_HIT              0x20
UMASK_ITLB_MISSES_WALK_COMPLETED        0x0E
UMASK_ITLB_MISSES_WALK_COMPLETED_4K     0x02
UMASK_ITLB_MISSES_WALK_COMPLETED_2M_4M  0x04
#UMASK_ITLB_MISSES_WALK_COMPLETED_1G     0x08
DEFAULT_OPTIONS_ITLB_MISSES_WALK_ACTIVE EVENT_OPTION_THRESHOLD=0x1
UMASK_ITLB_MISSES_WALK_ACTIVE           0x10

EVENT_ILD_STALL_LCP                 0x87 PMC
UMASK_ILD_STALL_LCP                 0x01

EVENT_IDQ_UOPS_NOT_DELIVERED            0x9C PMC
UMASK_IDQ_UOPS_NOT_DELIVERED_CORE       0x01
DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOPS_DELIV_CORE EVENT_OPTION_THRESHOLD=0x5
UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOPS_DELIV_CORE 0x01
DEFAULT_OPTIONS_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=0x1
UMASK_IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK 0x01

EVENT_UOPS_DISPATCHED_PORT              0xA1 PMC
UMASK_UOPS_DISPATCHED_PORT_PORT_0       0x01
UMASK_UOPS_DISPATCHED_PORT_PORT_1       0x02
UMASK_UOPS_DISPATCHED_PORT_PORT_2_3     0x04
UMASK_UOPS_DISPATCHED_PORT_PORT_4_9     0x10
UMASK_UOPS_DISPATCHED_PORT_PORT_5       0x20
UMASK_UOPS_DISPATCHED_PORT_PORT_6       0x40
UMASK_UOPS_DISPATCHED_PORT_PORT_7_8     0x80

EVENT_RESOURCE_STALLS                   0xA2 PMC
UMASK_RESOURCE_STALLS_SCOREBOARD        0x02
UMASK_RESOURCE_STALLS_SB                0x08

EVENT_CYCLE_ACTIVITY                    0xA3 PMC
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L1D_MISS EVENT_OPTION_THRESHOLD=0x8
UMASK_CYCLE_ACTIVITY_CYCLES_L1D_MISS    0x08
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L2_MISS EVENT_OPTION_THRESHOLD=0x1
UMASK_CYCLE_ACTIVITY_CYCLES_L2_MISS     0x01
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_L3_MISS EVENT_OPTION_THRESHOLD=0x2
UMASK_CYCLE_ACTIVITY_CYCLES_L3_MISS     0x02
DEFAULT_OPTIONS_CYCLE_ACTIVITY_CYCLES_MEM_ANY EVENT_OPTION_THRESHOLD=0x10
UMASK_CYCLE_ACTIVITY_CYCLES_MEM_ANY     0x10
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_TOTAL EVENT_OPTION_THRESHOLD=0x4
UMASK_CYCLE_ACTIVITY_STALLS_TOTAL       0x04
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L1D_MISS EVENT_OPTION_THRESHOLD=0xC
UMASK_CYCLE_ACTIVITY_STALLS_L1D_MISS    0x0C
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L2_MISS EVENT_OPTION_THRESHOLD=0x5
UMASK_CYCLE_ACTIVITY_STALLS_L2_MISS     0x05
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_L3_MISS EVENT_OPTION_THRESHOLD=0x6
UMASK_CYCLE_ACTIVITY_STALLS_L3_MISS     0x06
DEFAULT_OPTIONS_CYCLE_ACTIVITY_STALLS_MEM_ANY EVENT_OPTION_THRESHOLD=0x14
UMASK_CYCLE_ACTIVITY_STALLS_MEM_ANY     0x14

EVENT_TOPDOWN                           0xA4 PMC
UMASK_TOPDOWN_SLOTS_P                   0x01
UMASK_TOPDOWN_BACKEND_BOUND_SLOTS       0x02
UMASK_TOPDOWN_BR_MISPREDICT_SLOTS       0x08

EVENT_EXE_ACTIVITY                      0xA6 PMC
UMASK_EXE_ACTIVITY_1_PORTS_UTIL         0x02
UMASK_EXE_ACTIVITY_2_PORTS_UTIL         0x04
UMASK_EXE_ACTIVITY_3_PORTS_UTIL         0x08
UMASK_EXE_ACTIVITY_4_PORTS_UTIL         0x10
#UMASK_EXE_ACTIVITY_BOUND_ON_LOADS       0x21
UMASK_EXE_ACTIVITY_BOUND_ON_STORES      0x40
UMASK_EXE_ACTIVITY_EXE_BOUND_0_PORTS    0x80

EVENT_LSD_UOPS                          0xA8   PMC
UMASK_LSD_UOPS                          0x01
DEFAULT_OPTIONS_LSD_UOPS_CYCLES_ACTIVE EVENT_OPTION_THRESHOLD=0x01
UMASK_LSD_UOPS_CYCLES_ACTIVE            0x01
DEFAULT_OPTIONS_LSD_UOPS_CYCLES_OK EVENT_OPTION_THRESHOLD=0x05
UMASK_LSD_UOPS_CYCLES_OK                0x01

EVENT_DSB2MITE_SWITCHES_PENALTY_CYCLES 0xAB PMC
UMASK_DSB2MITE_SWITCHES_PENALTY_CYCLES 0x02
DEFAULT_OPTIONS_DSB2MITE_SWITCHES_PENALTY_COUNT EVENT_OPTION_THRESHOLD=0x01,EVENT_OPTION_EDGE=1
UMASK_DSB2MITE_SWITCHES_PENALTY_COUNT  0x02

EVENT_OFFCORE_REQUESTS                          0xB0 PMC
UMASK_OFFCORE_REQUESTS_DEMAND_DATA_RD           0x01
UMASK_OFFCORE_REQUESTS_DEMAND_RFO               0x04
UMASK_OFFCORE_REQUESTS_ALL_DATA_RD              0x08
UMASK_OFFCORE_REQUESTS_L3_MISS_DEMAND_DATA_RD   0x10
UMASK_OFFCORE_REQUESTS_ALL_REQUESTS             0x80

EVENT_UOPS_EXECUTED                         0xB1   PMC
UMASK_UOPS_EXECUTED_THREAD                  0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
UMASK_UOPS_EXECUTED_STALL_CYCLES            0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_1 EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_EXECUTED_CYCLES_GE_1             0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_2 EVENT_OPTION_THRESHOLD=0x2
UMASK_UOPS_EXECUTED_CYCLES_GE_2             0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_3 EVENT_OPTION_THRESHOLD=0x3
UMASK_UOPS_EXECUTED_CYCLES_GE_3             0x01
DEFAULT_OPTIONS_UOPS_EXECUTED_CYCLES_GE_4 EVENT_OPTION_THRESHOLD=0x4
UMASK_UOPS_EXECUTED_CYCLES_GE_4             0x01
UMASK_UOPS_EXECUTED_CORE                    0x02
#DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
#UMASK_UOPS_EXECUTED_CORE_STALL_CYCLES      0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_1 EVENT_OPTION_THRESHOLD=0x1
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_1        0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_2 EVENT_OPTION_THRESHOLD=0x2
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_2        0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_3 EVENT_OPTION_THRESHOLD=0x3
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_3        0x02
DEFAULT_OPTIONS_UOPS_EXECUTED_CORE_CYCLES_GE_4 EVENT_OPTION_THRESHOLD=0x4
UMASK_UOPS_EXECUTED_CORE_CYCLES_GE_4        0x02
UMASK_UOPS_EXECUTED_X87                     0x10

EVENT_TLB_FLUSH                         0xBD PMC
UMASK_TLB_FLUSH_DTLB_THREAD             0x01
UMASK_TLB_FLUSH_STLB_ANY                0x20

EVENT_INST_RETIRED                      0xC0 PMC
UMASK_INST_RETIRED_ANY                  0x00
UMASK_INST_RETIRED_ANY_P                0x00
UMASK_INST_RETIRED_STALL_CYCLES         0x01

EVENT_ASSISTS                           0xC1 PMC
UMASK_ASSISTS_FP                        0x02
UMASK_ASSISTS_ANY                       0x07

EVENT_UOPS_RETIRED                       0xC2  PMC
UMASK_UOPS_RETIRED_SLOTS                 0x02
DEFAULT_OPTIONS_RETIRED_STALL_CYCLES EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_INVERT=1
UMASK_UOPS_RETIRED_STALL_CYCLES          0x02
DEFAULT_OPTIONS_RETIRED_TOTAL_CYCLES EVENT_OPTION_THRESHOLD=0xA,EVENT_OPTION_INVERT=1
UMASK_UOPS_RETIRED_TOTAL_CYCLES          0x02

EVENT_MACHINE_CLEARS                    0xC3 PMC
DEFAULT_OPTIONS_MACHINE_CLEARS_COUNT    EVENT_OPTION_THRESHOLD=0x1,EVENT_OPTION_EDGE=0x1
UMASK_MACHINE_CLEARS_COUNT              0x01
UMASK_MACHINE_CLEARS_MEMORY_ORDERING    0x02
UMASK_MACHINE_CLEARS_SMC                0x04

EVENT_BR_INST_RETIRED                   0xC4 PMC
UMASK_BR_INST_RETIRED_ALL_BRANCHES      0x00
UMASK_BR_INST_RETIRED_COND_TAKEN        0x01
UMASK_BR_INST_RETIRED_NEAR_CALL         0x02
UMASK_BR_INST_RETIRED_NEAR_RETURN       0x08
UMASK_BR_INST_RETIRED_COND_NTAKEN       0x10
UMASK_BR_INST_RETIRED_COND              0x11
UMASK_BR_INST_RETIRED_NEAR_TAKEN        0x20
UMASK_BR_INST_RETIRED_FAR_BRANCH        0x40
UMASK_BR_INST_RETIRED_INDIRECT          0x80

EVENT_BR_MISP_RETIRED                   0xC5 PMC
UMASK_BR_MISP_RETIRED_ALL_BRANCHES      0x00
UMASK_BR_MISP_RETIRED_COND_TAKEN        0x01
UMASK_BR_MISP_RETIRED_INDIRECT_CALL     0x02
UMASK_BR_MISP_RETIRED_COND_NTAKEN       0x10
UMASK_BR_MISP_RETIRED_COND              0x11
UMASK_BR_MISP_RETIRED_NEAR_TAKEN        0x20
UMASK_BR_MISP_RETIRED_INDIRECT          0x80

#EVENT_FRONTEND_RETIRED                              0xC6 PMC
#UMASK_FRONTEND_RETIRED_DSB_MISS                     0x01 0x00 0x11
#UMASK_FRONTEND_RETIRED_L1I_MISS                     0x01 0x00 0x12
#UMASK_FRONTEND_RETIRED_L2_MISS                      0x01 0x00 0x13
#UMASK_FRONTEND_RETIRED_ITLB_MISS                    0x01 0x00 0x14
#UMASK_FRONTEND_RETIRED_STLB_MISS                    0x01 0x00 0x15
#UMASK_FRONTEND_RETIRED_LATENCY_GE_1                 0x01 0x00 0x500106 # Reg 0x3F7
#UMASK_FRONTEND_RETIRED_LATENCY_GE_2                 0x01 0x00 0x500206
#UMASK_FRONTEND_RETIRED_LATENCY_GE_4                 0x01 0x00 0x500406
#UMASK_FRONTEND_RETIRED_LATENCY_GE_8                 0x01 0x00 0x500806
#UMASK_FRONTEND_RETIRED_LATENCY_GE_16                0x01 0x00 0x501006
#UMASK_FRONTEND_RETIRED_LATENCY_GE_32                0x01 0x00 0x502006
#UMASK_FRONTEND_RETIRED_LATENCY_GE_64                0x01 0x00 0x504006
#UMASK_FRONTEND_RETIRED_LATENCY_GE_128               0x01 0x00 0x508006
#UMASK_FRONTEND_RETIRED_LATENCY_GE_256               0x01 0x00 0x510006
#UMASK_FRONTEND_RETIRED_LATENCY_GE_512               0x01 0x00 0x520006
#UMASK_FRONTEND_RETIRED_LATENCY_GE_2_BUBBLES_GE_1    0x01 0x00 0x100206

EVENT_FP_ARITH_INST_RETIRED                     0xC7 PMC
UMASK_FP_ARITH_INST_RETIRED_SCALAR_DOUBLE       0x01
UMASK_FP_ARITH_INST_RETIRED_SCALAR_SINGLE       0x02
UMASK_FP_ARITH_INST_RETIRED_128B_PACKED_DOUBLE  0x04
UMASK_FP_ARITH_INST_RETIRED_128B_PACKED_SINGLE  0x08
UMASK_FP_ARITH_INST_RETIRED_256B_PACKED_DOUBLE  0x10
UMASK_FP_ARITH_INST_RETIRED_256B_PACKED_SINGLE  0x20
UMASK_FP_ARITH_INST_RETIRED_512B_PACKED_DOUBLE  0x40
UMASK_FP_ARITH_INST_RETIRED_512B_PACKED_SINGLE  0x80

EVENT_HLE_RETIRED                       0xC8 PMC
UMASK_HLE_RETIRED_START                 0x01
UMASK_HLE_RETIRED_COMMIT                0x02
UMASK_HLE_RETIRED_ABORTED               0x04
UMASK_HLE_RETIRED_ABORTED_MEM           0x08
#UMASK_HLE_RETIRED_ABORTED_TIMER         0x10
UMASK_HLE_RETIRED_ABORTED_UNFRIENDLY    0x20
#UMASK_HLE_RETIRED_ABORTED_MEMTYPE       0x40
UMASK_HLE_RETIRED_ABORTED_EVENTS        0x80

EVENT_RTM_RETIRED                       0xC9 PMC
UMASK_RTM_RETIRED_START                 0x01
UMASK_RTM_RETIRED_COMMIT                0x02
UMASK_RTM_RETIRED_ABORTED               0x04
UMASK_RTM_RETIRED_ABORTED_MEM           0x08
UMASK_RTM_RETIRED_ABORTED_TIMER         0x10
UMASK_RTM_RETIRED_ABORTED_UNFRIENDLY    0x20
UMASK_RTM_RETIRED_ABORTED_MEMTYPE       0x40
UMASK_RTM_RETIRED_ABORTED_EVENTS        0x80

EVENT_MISC_RETIRED                      0xCC PMC
UMASK_MISC_RETIRED_LBR_INSERTS          0x20
UMASK_MISC_RETIRED_PAUSE_INST           0x40

#EVENT_MEM_TRANS_RETIRED                         0xCD PMC
#UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_4       0x01 0x00 0x04 #0x3F6
#UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_8       0x01 0x00 0x08
#UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_16      0x01 0x00 0x10
#UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_32      0x01 0x00 0x20
#UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_64      0x01 0x00 0x40
#UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_128     0x01 0x00 0x80
#UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_256     0x01 0x00 0x100
#UMASK_MEM_TRANS_RETIRED_LOAD_LATENCY_GT_512     0x01 0x00 0x200

EVENT_MEM_INST_RETIRED                  0xD0 PMC
UMASK_MEM_INST_RETIRED_STLB_MISS_LOADS  0x11
UMASK_MEM_INST_RETIRED_STLB_MISS_STORES 0x12
UMASK_MEM_INST_RETIRED_LOCK_LOADS       0x21
UMASK_MEM_INST_RETIRED_SPLIT_LOADS      0x41
UMASK_MEM_INST_RETIRED_SPLIT_STORES     0x42
UMASK_MEM_INST_RETIRED_ALL_LOADS        0x81
UMASK_MEM_INST_RETIRED_ALL_STORES       0x82
UMASK_MEM_INST_RETIRED_ALL              0x83

EVENT_MEM_LOAD_RETIRED                  0xD1 PMC
UMASK_MEM_LOAD_RETIRED_L1_HIT           0x01
UMASK_MEM_LOAD_RETIRED_L2_HIT           0x02
UMASK_MEM_LOAD_RETIRED_L3_HIT           0x04
UMASK_MEM_LOAD_RETIRED_L1_MISS          0x08
UMASK_MEM_LOAD_RETIRED_L2_MISS          0x10
UMASK_MEM_LOAD_RETIRED_L3_MISS          0x20
UMASK_MEM_LOAD_RETIRED_FB_HIT           0x40
UMASK_MEM_LOAD_RETIRED_L1_ALL           0x09
UMASK_MEM_LOAD_RETIRED_L2_ALL           0x12
UMASK_MEM_LOAD_RETIRED_L3_ALL           0x24

EVENT_MEM_LOAD_L3_HIT_RETIRED           0xD2 PMC
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_MISS 0x01
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_HIT  0x02
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_HITM 0x04
UMASK_MEM_LOAD_L3_HIT_RETIRED_XSNP_NONE 0x08

EVENT_BACLEARS                      0xE6 PMC
UMASK_BACLEARS_ANY                  0x01

EVENT_CPU_CLOCK_UNHALTED_REF_DISTRIBUTED    0xEC PMC
UMASK_CPU_CLOCK_UNHALTED_REF_DISTRIBUTED    0x02

# The only officially released event is L2_TRANS_L2_WB
# All others count something but no guarantees
EVENT_L2_TRANS                0xF0  PMC
UMASK_L2_TRANS_DEMAND_DATA_RD 0x01
UMASK_L2_TRANS_RFO            0x02
UMASK_L2_TRANS_CODE_RD        0x04
UMASK_L2_TRANS_ALL_PF         0x08
UMASK_L2_TRANS_L1D_WB         0x10
UMASK_L2_TRANS_L2_FILL        0x20
UMASK_L2_TRANS_L2_WB          0x40
UMASK_L2_TRANS_ALL_REQUESTS   0x80

EVENT_L2_LINES_IN                       0xF1 PMC
#UMASK_L2_LINES_IN_I                     0x01
#UMASK_L2_LINES_IN_S                     0x02
#UMASK_L2_LINES_IN_E                     0x04
UMASK_L2_LINES_IN_ALL                   0x1F

EVENT_L2_LINES_OUT                      0xF2 PMC
UMASK_L2_LINES_OUT_SILENT               0x01
UMASK_L2_LINES_OUT_NON_SILENT           0x02
UMASK_L2_LINES_OUT_USELESS_HWPF         0x04

EVENT_SQ_MISC                       0xF4 PMC
UMASK_SQ_MISC                       0x04

